1 pi6lc48l0201 block diagram description te pi6lc48l0201 is a 2-output lvds synthesizer optimized to generate ethernet reference clock frequencies and is a member of pericoms hiflex family of high performance clock solutions. using a 25mhz crystal, the most popular ethernet frequencies can be generated based on the settings of 2 frequency select pins. te pi6lc48l0201 uses pericoms proprietary low phase noise pll technology to achieve ultra low phase jitter, so it is ideal for ethernet interface in all kind of systems. features ? ? two diferential lvds output pairs ? ? selectable crystal oscillator interface or lvcmos/lvttl single-ended clock input ? ? supports the following output frequencies: 62.5mhz, 125mhz, 156.25mhz ? ? rms phase jitter @ 156.25mhz, using a 25mhz crystal (1.875mhz C 20mhz): 0.2ps (typical) ? ? rms phase jitter @ 156.25mhz, using a 25mhz crystal (12khz C 20mhz): 0.32ps (typical) ? ? full 3.3v or 2.5v supply modes ? ? commercial and industrial ambient operating temperature ? ? available in lead-free package: 20-tssop applications ? ? networking systems 2-output lvds networking clock generator pfd vco m osc xtal_out xtal_in ref_in in_sel pll_bypass /n m_reset n_sel[0:1] clk0 clk0# clk1 clk1# www.pericom.com pi6lc48l0201 rev . a 07/23/2013 13-0115
2 pinout table pin no. pin name i/o ty pe description 1, 7, 16 nc no connection 2, 20 vddo power - output power supply 3,4 clk0, clk0# output - lvds output clock 0 5 m_reset input pull-down master reset. 1, clk0clk1 go to low, clk0#/clk1# go to high; 0 outputs are enabled 6 pll_bypass input pull-down pll bypass select. 0 pll is enabled, 1 pll is bypassed 8 vdda power - analog power supply 9, 11 n_sel0, n_sel1 input pull-down output frequency select 10 vdd power - core power supply 12, 13 xtal_out, xtal_in crystal - crystal input and output 14 ref_in input pull-down cmos reference clock input 15 in_sel input pull-down 0 selects crystal, 1 selects reference input 17 gnd ground - ground 18, 19 clk1#, clk1 output - lvds output clock 1 pin configuration 1 2 3 vdda 4 clk1 5 m_reset 6 7 ref_in 8 clk1# clk0 clk0# in_sel 20 19 18 17 nc pll_bypass vddo xtal_in 9 n_sel0 16 xtal_out 10vdd 15 gnd 11 nc 14 12 13 n_sel1 nc vddo www.pericom.com pi6lc48l0201 rev . a 07/23/2013 pi6lc48l0201 2-output lvds networking clock generator 13-0115
3 output frequency selection table xtal frequency n_sel1 n_sel0 output frequency 25 00 156.25 01 125 10 62.5 11 reserved typical crystal requirement parameter minimum ty pica l maximum units mode of oscillation fundamental frequency 22.4 25 27.2 mhz equivalent series resistance (esr) 50 shunt capacitance 7 pf drive level 1 mw recommended crystal specification pericom recommends: a) fl2500047, smd 3.2x2.5(4p), 25mhz, cl=18pf, +/-20ppm, http://www.pericom.com/pdf/datasheets/se/fl.pdf b) fy2500091, smd 5x3.2(4p), 25mhz, cl=18pf, +/-30ppm, http://www.pericom.com/pdf/datasheets/se/fy_f9.pdf www.pericom.com pi6lc48l0201 rev . a 07/23/2013 pi6lc48l0201 2-output lvds networking clock generator 13-0115
4 maximum ratings (over operating free-air temperature range) note: stresses greater than those listed under maximum ratings may cause permanent damage to the device. tis is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specifcation is not implied. exposure to absolute maximum rating conditions for extended periods may afect reliability. storage temperature .............................................. -65oc to+155oc ambient temperature with power applied ......... -40oc to+85oc 3.3v analog supply voltage ...................................... -0.5 to +3.6v esd protection (hbm) ......................................................... 2000v dc electrical characteristics power supply dc characterisitcs, (t a = -40oc to 85oc) symbol parameter condition min ty p max units v dd , v dda , v ddo core supply voltage 3.135 3.3 3.465 v v dd , v dda , v ddo analog supply voltage 2.375 2.5 2.625 v i dd power supply current v dd =v dda = v ddo = 3.3v +/-5% 105 ma v dd =v dda = v ddo = 2.5v +/-5% 98 i dda analog supply current v dd =v dda = v ddo = 3.3v +/-5% 26 ma v dd =v dda = v ddo = 2.5v +/-5% 26 i ddo output supply current v dd =v dda = v ddo = 3.3v +/-5% 55 ma v dd =v dda = v ddo = 2.5v +/-5% 55 lvcmos/lvttl dc characterisitcs, (t a = -40oc to 85oc) symbol parameter condition min ty p max units v ih input high voltage v dd = 3.3 v +/- 5% 2 v dd + 0.3 v v dd = 2.5 v +/- 5% 1.7 v dd + 0.3 v v il input low voltage v dd = 3.3 v +/- 5% -0.3 0.8 v v dd = 2.5 v +/- 5% -0.3 0.7 v i ih input high current m_reset, pll_bypass, n_ sel[0:1], in_sel, ref_in v dd = vin = 3.465v 150 a i il input low current m_reset, pll_bypass, n_ sel[0:1], in_sel, ref_in v dd = 3.465v, v in = 0v -5 a pin characterisitcs symbol parameter condition min ty p max units c in input capacitance 4 pf r pulldownn pull down resistor 51 k www.pericom.com pi6lc48l0201 rev . a 07/23/2013 pi6lc48l0201 2-output lvds networking clock generator 13-0115
5 lvds dc characterisitcs, (t a = -40oc to 85oc) symbol parameter condition min ty p max units v od diferential output voltage v dd = 3.3v 247 454 mv v dd = 2.5v 247 454 d v od change of v od v dd = 3.5v 50 mv v dd = 2.5v 50 v os output ofset voltage v dd = 3.3v 1.125 1.375 v v dd = 2.5v 1.125 1.375 d v os change of v os v dd = 3.5v 50 mv v dd = 2.5v 50 ac electrical characteristics, (t a = -40oc to 85oc) symbol parameter condition min. ty p. max units f out output frequency n_sel[1:0] = 00 140 170 mhz n_sel[1:0] = 01 112 136 mhz n_sel[1:0] = 10 56 68 mhz t sk(o) output skew (1, 3) outputs @ same loading 50 ps t jit(?) rms phase jitter, (random) (2) 156.25mhz, (1.875mhz - 20mhz) 0.2 ps 156.25mhz, (12khz - 20mhz) 0.32 ps 125mhz, (1.875mhz - 20mhz) 0.2 ps 125mhz, (12khz - 20mhz) 0.31 ps 62.5mhz, (1.875mhz - 20mhz) 0.4 ps 62.5mhz, (12khz - 20mhz) 0.5 ps t r / t f output rise/fall time 20% to 80% 400 ps odc output duty cycle 48 52 % note: 1. defned as skew within a bank of outputs at the same supply voltage and with equal load conditions. measured at the diferential cross points. 2. please refer to the phase noise plots. 3. tis parameter is defned in accordance with jedec standard 65. www.pericom.com pi6lc48l0201 rev . a 07/23/2013 pi6lc48l0201 2-output lvds networking clock generator 13-0115
6 phase noise plots f out = 156.25mhz f out = 125mhz f out = 62.5mhz www.pericom.com pi6lc48l0201 rev . a 07/23/2013 pi6lc48l0201 2-output lvds networking clock generator 13-0115
7 100 z = 50 o z = 50 o lv ds buffer v ddo l = 0 ~ 10 in. lvds test circuit power supply filtering techniques as in any high speed analog circuitry, the power supply pins are vulnerable to random noise. to achieve optimum jitter perfor - mance, power supply isolation is required. te pi6lc48l0201 provides separate power supplies to isolate any high switching noise from the outputs to the internal pll. v dd , v dda and v ddo should be individually connected to the power supply plane through vias, and 0.1f bypass capacitors should be used for each pin. figure below illustrates this for a generic v dd pin and also shows that v dda requires that an additional 10 resistor along with a 10f bypass capacitor be connected to the v dda pin. v dd 0.1f 0.1f 10f 10? * 3.3v or 2.5v v dda * if v dd is 2.5v, the resistor value will be di erent, see app note for details www.pericom.com pi6lc48l0201 rev . a 07/23/2013 pi6lc48l0201 2-output lvds networking clock generator 13-0115
8 recommendations for unused input and output pins inputs: crystal inputs: for applications not requiring the use of the crystal oscillator input, both xtal_in and xtal_out can be lef foating. a 1k resistor can be tied from xtal_in to ground for additional protection. ref_in input: for applications not requiring the use of the clock, it can be lef foating. a 1k resistor tied from the ref_in to ground can provide additional protection. lvcmos control pins: all control pins have internal pulldowns; a 1k resistor tied from each control pin to ground can provide additional protection. outputs: lvds outputs: all unused lvds output pairs can be either lef foating or terminated with 100 across. if they are lef foating, we recommend that there is no trace attached. crystal input interface te clock generator has been characterized with 18pf parallel resonant crystals. te capacitor values shown in the fgure below were determined using a 25mhz, 18pf parallel resonant crystal and were chosen to minimize the ppm error. c1 22pf c2 22pf xtal_in xtal_out x1 18pf parallel crystal www.pericom.com pi6lc48l0201 rev . a 07/23/2013 pi6lc48l0201 2-output lvds networking clock generator 13-0115
9 lvcmos to xtal interface te xtal_in input can accept a single-ended lvcmos signal through an ac coupling capacitor. a general interface diagram is shown in the fgure below. te xtal_out pin can be lef foating. te input edge rate can be as slow as 10ns. for lvcmos signals, it is recommended that the amplitude be reduced from full swing to half swing in order to prevent signal interference with the power rail and to reduce noise. tis confguration requires that the output impedance of the driver (ro) plus the series resis - tance (rs) equals the transmission line impedance. in addition, matched termination at the crystal input will attenuate the signal in half. tis can be done in one of the two ways. first, r1 and r2 in parallel should equal the transmission line empedance. for most 50 applications, r1 and r2 can be 100 . this can also be accomplished by removing r1 and making r2 50. by overdriving the crystal oscillator, the device will be functional, but note, the device performance is quaranteed by using a quartz crystal. v r2 50 dd ro rs zo = ro + rs r1 xtal_in xtal_out v dd 0.1f thermal information symbol description condition ja junction-to-ambient thermal resistance still air 84.0 o c/w 4 jc junction-to-case thermal resistance 17.0 o c/w www.pericom.com pi6lc48l0201 rev . a 07/23/2013 pi6lc48l0201 2-output lvds networking clock generator 13-0115
10 ordering information ordering code packaging type package description operating temperature PI6LC48L0201LE l pb-free & green, 20-pin tssop commercial pi6lc48l0201lie l pb-free & green, 20-pin tssop industrial notes: ? termal characteristics can be found on the company web site at www.pericom.com/packaging/ ? "e" denotes pb-free and green ? adding an "x" at the end of the ordering code denotes tape and reel packaging pericom semiconductor corporation ? 1-800-435-2336 ? www .pericom.com packaging mechanical: 20-contact tssop (l) date: 05/03/12 description: 20-pin, 173mil wide tssop package code: l document control #: pd-1311 revision: f notes: 1. refer jedec mo-153f/ac 2. controlling dimensions in millimeters 3. package outline exclusive of mold flash and metal burr 12-0373 www.pericom.com pi6lc48l0201 rev . a 07/23/2013 pi6lc48l0201 2-output lvds networking clock generator 13-0115
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